1. Field of the Invention
The present invention relates to a semiconductor memory such as a dynamic RAM.
2. Description of the Related Art
FIG. 5 shows part of a circuit for a conventional semiconductor memory (one of memory blocks), including a memory cell array 1, a row decoder 2, a column predecoder 3, column decoders 4, a main amplifier 20, an output circuit 6, word lines 30, bit-line pairs 31 (each consisting of bit lines 31A and 31B), and a data-line pair 32 (consisting of data lines 32A and 32B), etc.
The memory block of FIG. 5 has 256 column decoders and 256 bit-line pairs.
The row decoder 2 selectively sets a word line 30 among the plurality of word lines 30 active in accordance with input row addresses. Herein, the phrase "to set a signal line active" means "to set a signal line into a logically activated state or a selected state, by setting the potential of the signal line to a certain value". Similarly, the phrase "to set a signal line inactive" used herein means "to set a signal line into a logically inactivated state or a non-selected state, by setting the potential of the signal line to another certain value".
The column predecoder 3 selectively sets one signal line active in each of four signal-line sets (CA01, CA23, CA45, and CA67), in accordance with the input column addresses (CA0 to CA7). Each of the signal-line sets consists of four signal lines. Depending on the combination of the signal lines which are selectively set active by the column predecoder 3, any one of 0th to 255th column decoders is selected. A column signal line 47 which is connected to the selected column decoder is set active. At this time, a switching transistor pair 34 which is connected to the activated column signal line 47 is turned ON, so that the bit-line pair 31 corresponding to the selected column decoder and the data-line pair 32 are electrically connected to each other.
A bit line precharge signal generating circuit 7 generates a bit line precharge signal. In accordance with the bit line precharge signal, each electric potential of the bit lines 31A and 31B is precharged up to 1/2 V.sub.cc, where V.sub.cc represents a power supply potential.
When the bit line pair 31 is being precharged, a sense amplifier driving signal generating circuit 8 sets each electric potential of a PMOS sense amplifier driving signal line 48 and an NMOS sense amplifier driving signal line 49 to 1/2 V.sub.cc. Where the sense amplifier 9 operates, the sense amplifier driving signal generating circuit 8 sets the electric potential of the PMOS sense amplifier driving signal line 48 to V.sub.cc, and the potential of the NMOS sense amplifier driving signal line 49 to GND.
The sense amplifier 9 amplifies the electric potential difference read out from the memory cell 33 to the bit-line pair 31.
The main amplifier 20 amplifies the electric potential difference of the data-line pair 32. An output circuit 6 outputs a signal for identifying the data stored in the memory cell 33 at an output terminal 35 in accordance with the output of the main amplifier 20.
A timing generating circuit 10 sets signal lines 51 to 55 active at a predetermined timing. The signal lines 51 to 55 are connected to the row decoder 2, the bit line precharge signal generating circuit 7, the sense amplifier driving signal generating circuit 8, the column predecoder 3, and the main amplifier 20, respectively.
FIG. 6 shows an exemplary configuration of the conventional main amplifier 20 and the output circuit 6. The main amplifier 20 includes two differential amplifiers 60 and 61. FIG. 7 shows an exemplary configuration of the conventional differential amplifier 60. As shown in FIG. 7, the differential amplifier 60 includes an NMOS transistor 80 connected to a negative input terminal 63B, an NMOS transistor 81 connected to a positive input terminal 63A, and a transistor 84 for pulling down the electric potential of a junction 88 between the source of the NMOS transistor 80 and the source of the NMOS transistor 81. The differential amplifier 61 has the same structure as the differential amplifier 60 does.
Hereinafter, an operation of the differential amplifier 60 will be described in the following cases (1) and (2). The differential amplifier 61 operates in the same manner as the differential amplifier 60 does.
(1) When an electric potential of an activating signal input into an activating terminal 62 of the main amplifier 20 is at a low level (L), an electric potential of a signal output from an output terminal 69 of the differential amplifier 60 is set to be at a low level (L).
(2) When the electric potential of the activating signal input into the activating terminal 62 of the main amplifier 20 is at a high level (H), the electric potential of the signal output from the output terminal 69 of the differential amplifier 60 is determined on the basis of the relationship between electric potentials of the signals input into the positive input terminal 63A and the negative input terminal 63B as follows:
(a) When the electric potential of the signal input into the positive input terminal 63A is higher than that of the signal input into the negative input terminal 63B, the electric potential of the signal output from the output terminal 69 of the differential amplifier 60 is set to be at a high level (H). PA1 (b) When the electric potential of the signal input into the positive input terminal 63A is lower than that of the signal input into the negative input terminal 63B, the electric potential of the signal output from the output terminal 69 of the differential amplifier 60 remains at the low level (L).
When the signal line 55 is set to be active, the electric potential of the activating signal input into the activating terminal 62 is turned to a high level (H). Therefore, the differential amplifiers 60 and 61 operate according to the case (2) described above.
In FIG. 6, each of main amplifier output lines 37A and 37B is precharged to reach a high level (H) by an output circuit precharge signal which is input via a terminal 66. Herein, it is assumed that when the main amplifier output lines 37A and 37B are set to be active, the electric potentials thereof are at a low level (L); and when they are set to be inactive, the electric potentials thereof are at a high level (H). Furthermore, the output circuit 6 outputs data H to the output terminal 35 when the electric potential of the main amplifier output line 37A is turned to a low level (active state); and the output circuit 6 outputs data L to the output terminal 35 when the electric potential of the main amplifier output line 37B is turned to a low level (active state). That is, a state where the main amplifier output line 37A is set to be active (L) corresponds to data H; and a state where the main amplifier output line 37B is set to be active (L) corresponds to data L.
When the activating signal is input via the activating terminal 62, the main amplifier 20 amplifies the electric potential difference between the data lines 32A and 32B, and then outputs a signal having the amplified electric potential difference to the main amplifier output lines 37A and 37B, respectively.
Hereinafter, the operation of the main amplifier 20 will be described in the following cases (1) and (2).
(1) When an electric potential of the data line 32A is higher than that of the data line 32B, the electric potential of the signal output from the differential amplifier 60 is set to be at a high level (H), and the electric potential of the signal output from the differential amplifier 61 is set to be at a low level (L). As a result, the electric potential of the main amplifier output line 37A is reduced to a low level (active state), and the electric potential of the main amplifier output line 37B remains at the high level (inactive state). At this time, the output circuit 6 outputs the data H to the output terminal 35.
(2) When the electric potential of the data line 32A is lower than that of the data line 32B, the electric potential of the signal output from the differential amplifier 60 is set to be at a low level (L), and the electric potential of the signal output from the differential amplifier 61 is set to be at a high level (H). As a result, the electric potential of the main amplifier output line 37A remains at the high level (inactive state), and the electric potential of the main amplifier output line 37B is reduced to a low level (active state). At this time, the output circuit 6 outputs the data L to the output terminal 35.
When the main amplifiers output lines 37A and 37B are precharged, i.e., when each electric potential of the main amplifier output lines 37A and 37B is at a high level (H), the output terminal 35 has a higher impedance. When the electric potential of the main amplifier output line 37A is reduced to a low level (active state), the output circuit 6 outputs an output signal having a high level (H) of electric potential from the output terminal 35. On the other hand, when the electric potential of the main amplifier output line 37B is reduced to a low level (active state), the output circuit 6 outputs an output signal having a low level (L) of electric potential from the output terminal 35.
FIG. 8 shows electric potential variations of various signal lines during the operation of the semiconductor memory in which the conventional differential amplifiers 60 and 61 of FIG. 6 are included in the main amplifier 20. In FIG. 8, the horizontal axis represents time, and the vertical axis represents voltage. In this conventional example, the data read out from the memory cell 33 is assumed to be at a low level (L).
The timing generating circuit 10 sets the signal line 52 inactive, and the signal lines 51, 53, 54, and 55 active, respectively. As a result, each electric potential of these signal lines 51 to 55 changes as shown in FIG. 8.
When the signal line 52 is set to be inactive, the bit line precharge signal generating circuit 7 makes the electric potential of the bit line precharge signal to the low level (L).
When the signal line 51 is set to be active, the row decoder 2 selectively makes one word line 30 active in accordance with the input row addresses.
When the signal line 53 is set to be active, the sense amplifier driving signal generating circuit 8 changes the electric potential of the PMOS sense amplifier driving signal line 48 from 1/2 V.sub.cc into V.sub.cc (power supply electric potential), and also changes the electric potential of the NMOS sense amplifier driving signal line 49 from 1/2 V.sub.cc to GND.
When the signal line 54 is set to be active, the column predecoder 3 selectively makes one of four signal lines active in the signal-line set CA01, in accordance with the input column addresses (CA0 to CA7). As described above, one of four signal lines of each of the other three signal-line sets (CA23, CA45, and CA67) has already been selectively set to be active.
The column decoder 4 sets a column signal line 47 active at the same time when one signal line in the signal line set CA01 is selectively set to be active, depending on the combination of signal lines which are selectively set active by the column predecoder 3. When the switching transistor pair 34 which is connected to the column signal line 47 is turned to ON, the bit-line pair 31 and the data-line pair 32 are electrically connected to each other.
When the signal line 55 is set to be active, the main amplifier 20 amplifies the electric potential difference which is transmitted to the data-line pair 32. In FIG. 8, the electric potential of the data line 32A is higher than that of the data line 32B, so that the electric potential of the main amplifier output line 37B is reduced to a low level (L). On the other hand, the electric potential of the main amplifier output line 37A remains at the high level (H) (i.e., remains at V.sub.cc).
Conventionally, the signal line 55 for activating the main amplifier 20 must be set active after a predetermined period of time after the column signal line 47 is set to be active. This is because the main amplifier 20 should be prevented from being activated until the electric potential difference between the data lines 32A and 32B becomes sufficiently large. If the main amplifier 20 is activated before the electric potential difference between the data lines 32A and 32B becomes sufficiently large, there is a possibility that the main amplifier 20 will output wrong data due to the low amount of electric potential difference between the data lines 32A and 32B to be input into the main amplifier 20.
According to the conventional semiconductor memory, a delay time should previously be set, from a time when the column signal line 47 is set to be active to a time when the signal line 55 for activating the main amplifier 20 is set to be active. That is, the main amplifier 20 should be prevented from being activated until the electric potential difference between the data lines 32A and 32B becomes sufficiently large. Furthermore, when the above-mentioned delay time or a period of time required for making the electric potential difference between the data lines 32A and 32B sufficiently large varies widely, the main amplifier 20 may be activated before the electric potential difference between the data lines 32A and 32B becomes sufficiently large, so that there is a possibility that the main amplifier 20 will output wrong data. Even when the above mentioned delay time is set to have sufficient margin in order to avoid such a problem, there arises another problem in that the access time of the semiconductor memory is inevitably increased due to the unnecessary long delay time.